Parallax Propeller Microcontroller

microcontrollers, Parallax Propeller microcontroller, Multi-core architecture of Parallax Propeller, Speed and power management , On-board peripherals, ROM extensions , Built in SPIN byte code interpreter , Example program , Package and I/O , Dedicated cores instead of interrupts

Parallax Propeller Microcontroller


The microcontroller Parallax P8X32 Propeller microcontroller was introduced in 2006. It has multi-core architecture. It is parallel microcontroller. It has eight 32-bit RISC CPU cores.

The Propeller Assembly language, Parallax Propeller microcontroller and Spin interpreter were designed by the same person. The founder Parallax propeller is Chip Gracey. The Spin Programming language and “Propeller Tool” were designed by Chip Gracey and Jeff Martin. The Propeller is very famous for being to program it.

Multi-core architecture of Parallax Propeller:

In Parallax Propeller microcontrollers, each of the eight 32-bit cores has a Central Processing Unit which has full access to 512 32-bit long words of instructions and data. The possibility of self-modifying code is usually internally, e.g. by an instruction which is being used to make a subroutine mechanism without having need of stack. In Parallax Propeller microcontrollers, the access to shared memory is controlled in round-robin fashion by an internal bus controller which is called the hub.  Each cog (eight 32-bit cores) also has easy access to two special “video registers” and two dedicated hardware counters for use in generating VGA, PAL, NTSSC, servo-control, or other timing signals.

Speed and power management:

The Parallax Propeller microcontroller can be clocked by using either an internal, on chip oscillator or an external crystal or resonator. Only the external oscillator may be run through an on chip PLL clock multiplier, which can be set at 1x, 2x, 4x,………… 16x.

Both the on board oscillator frequency and the PLL multiplier value can be changed at run time. If these are used correctly, then this can improve power efficiency: e.g. the PLL multiplier may be decreased before a long” no operation” and wait is required for timing purposes, then increased afterwards, causing the processor to use less power.

The utility of this operation is very limited to situation where no other cog is executing timing dependent code, since the effective clock rate is common to all cogs.

The effective ranges are from 32 kHz to 80 MHz (with dynamic configuration). When it runs at 80 MHz the proprietary interpreted Spin Programming language executed at approximately 80,000 instruction-tokens /sec on each core, giving 8 times 80,000 for 640,000 high level instructions/sec .  Most machine languages instructions take 4 clock cycles to execute, resulting in 20 MIPS per cog, or 160 MIPS in total for an 8-cog Propeller

On-board peripherals of Parallax Propeller :

Each cog has access to some dedicated counter/timer hardware, and a special timing signal generator intended to simplify the design of video output stages, such as composite PAL or NTSC displays (including modulation for broadcast) and VGA monitors. Parallax thus makes sample code available which can generate video signals (text and somewhat low-resolution graphics) using a minimum parts count consisting of the Propeller, a crystal oscillator, and a few resistors to form a crude DAC. The frequency of the oscillator is important, as the correction ability of the video timing hardware is limited to the clock rate. It is possible to use multiple cogs in parallel to generate a single video signal. More generally, the timing hardware can be used to implement various pulse-width modulated (PWM) timing signals

ROM extensions:

  • In addition to the Spin interpreter and a boot loader, the built-in ROM provides some data which may be useful for certain sound, video, or mathematical applications:
  • a bitmap font is provided, suitable for typical character generation applications (but not customizable);
  • a logarithm table (base 2, 2048 entries);
    • an antilog table (base 2, 2048 entries); and
    • a sine table (16-bit, 2049 entries).

The math extensions are intended to help compensate for the lack of a floating-point unit as well as more primitive missing operations, such as multiplication and division (this is masked in Spin but is a limitation for assembly language routines). The Propeller is a 32-bit processor, however, and these tables may not have sufficient accuracy for higher-precision applications.

Built in SPIN byte code interpreter

Spin is a multitasking high level computer programming language created by Parallax’s Chip Gracey, who also designed the Propeller microcontroller on which it runs, for their line of Propeller microcontrollers.

Spin code is written on the Propeller Tool, a GUI oriented software development platform written for Windows XP.  This compiler converts the Spin code into bytecodes that can be loaded (with the same tool) into the main 32 KB RAM, and optionally into the serial boot FLASH EEPROM, of the Propeller chip. After booting the propeller microcontrollers , a byte code interpreter is copied from the built in ROM into the 2 KB RAM of the primary COG. This COG will then start interpreting the byte codes in the main 32 KB RAM. More than one copy of the bytecode interpreter can run in other COGs, so several Spin code threads can run simultaneously. Within a Spin code program, assembler code program(s) can be “inline” inserted. These assembler program(s) will then run on their own COG’s.

Like Python, Spin uses indentation/whitespace, rather than curly braces or keywords, to delimit blocks.

The Propeller’s interpreter for its proprietary multi-threaded SPIN computer language is a byte code interpreter. This interpreter decodes strings of instructions, one instruction per byte, from user code which has been edited, compiled, and loaded onto the Propeller from within a purpose-specific IDE. This IDE, which Parallax simply calls “The Propeller tool”, is intended for use under the Windows operating system.

The SPIN language is a high level language. Because it is interpreted in software, it runs slower than pure Propeller assembly but can be more space-efficient (Propeller assembly opcodes are 32 bits long; SPIN directives are 8 bits long, which may be followed by a number of 8-bit bytes to specify how that directive operates). SPIN also allows users to avoid significant memory segmentation issues that must be considered for assembly code.

Mixing SPIN and assembly code is straightforward; SPIN is more appropriate for high-level logic, while assembly routines may be required for I/O routines that require exact timing.

At startup, a copy of the byte code interpreter (less than 2 KB in size), will be copied into the dedicated RAM of a cog and will then start interpreting byte code in the main 32 KB RAM. Additional cogs can be started from that point, loading a separate copy of the interpreter into the new cog’s dedicated RAM (a total of eight interpreter threads can, therefore, run simultaneously). Notably, this means that at least a minimal amount of startup code must be SPIN code, for all Propeller applications.

Example program

An example program, (as it would appear in the “Propeller Tool” editor) which outputs the current system counter every 3,000,000 cycles, then is shut down by another cog after 40,000,000 cycles:

microcontrollers, Parallax Propeller microcontroller, Multi-core architecture of Parallax Propeller, Speed and power management , On-board peripherals, ROM extensions , Built in SPIN byte code interpreter , Example program , Package and I/O , Dedicated cores instead of interrupts

Parallax Propeller example program

The Parallax Propeller is gradually accumulating software libraries which give it similar functionality to Parallax’s older BASIC Stamp product; however there is no uniform list of which PBASIC facilities now have Spin equivalents.

Package and I/O :

The initial version of the chip (called the P8X32) provides one 32 bit port in a 40-pin 0.6 DIP, 44-pin LQFP, or QFN package. Of the 40 available pins, 32 are used for I/O, four for power and ground pins, two for an external crystal (if used), one to enable brownout-detection, and one for reset.

All 8 cores can access the 32-bit port (designated “A”; there is currently no “B”) simultaneously. A special control mechanism is used to avoid I/O conflicts if one core attempts to use an I/O pin as an output while another tries to use it as input. Any of these pins can be used for the timing or pulse-width modulation output techniques described above.

Parallax has stated that it expects later versions of the Propeller to offer more I/O pins and/or more memory.

The Propeller’s designers designed it around the concept of “virtual I/O devices”. For example, the “HYDRA Game Development Kit”, (a computer system designed for hobbyists, to learn to develop “retro-style” video games) uses the built in character generator and video support logic to generate a virtual Video display generator that outputs VGA colour pictures, PAL/NTSC compatible colour pictures or broadcast RF video+audio in software

The screen capture displayed here was made using a software “virtual display driver” that sends the pixel data over a serial link to a PC.

Software libraries are available to implement several I/O devices ranging from simple UARTs and Serial I/O interfaces such as SPI, I2C and PS/2 compatible serial mouse and keyboard interfaces, motor drivers for robotic systems, MIDI interfaces and LCD controllers

Dedicated cores instead of interrupts:

The design philosophy of the Propeller is that a hard real-time, multi-core architecture negates the need for dedicated interrupt hardware and support in assembly. In traditional CPU architecture external interrupt lines are fed to an on-chip interrupt controller and serviced by one or more interrupt service routines. When an interrupt occurs the interrupt controller suspends normal CPU processing and saves internal state (typically on the stack) then vectors to the designated interrupt service routine. After handling the interrupt the service routine executes a “return from interrupt” instruction which restores the internal state and resumes CPU processing.

To handle an external signal promptly on the Propeller, any one of the 32 I/O lines is configured as an input. A cog is then configured to wait for a transition (either positive or negative edge) on that input using one of the two counter circuits available to each cog. While waiting for the signal, the cog operates in low-power mode, essentially sleeping. Extending this technique, a Propeller can be set up to respond to eight independent “interrupt” lines with essentially zero handling delay. Alternately, a single line can be used to signal the “interrupt” and then additional input lines can be read to determine the nature of the event. The code running in the other cores is not affected by the interrupt handling cog. Unlike a traditional multitasking single-processor interrupt architecture, the signal response timing remains predictable, and indeed using the term “interrupt” in this context can cause confusion, since this functionality can be more properly thought of as polling with a zero loop time.

Boot mechanism:

On power up, brownout detection, software reset, or external hardware reset, the Propeller will load a machine-code boot routine from the internal ROM into the RAM of its first (primary) cog and execute it. This code emulates an I2C interface in software, temporarily using two I/O pins for the needed serial clock and data signals to load user code from an external I2C EEPROM.

Simultaneously, it emulates a serial port, using two other I/O pins that can be used to upload software directly to RAM (and optionally to the external EEPROM). If the Propeller does not see any commands from the serial port, it will load the user program (the entry code of which must be written in SPIN, as described above) from the serial EEPROM into the main 32K RAM. After that it will load the SPIN interpreter from its built-in ROM into the dedicated RAM of its first cog, thereby overwriting most of the bootloader.

Regardless of how the user program is loaded, execution starts by interpreting initial user bytecode with the SPIN interpreter running in the primary cog. After this initial SPIN code runs, the application can turn on any unused cog to start a new thread, and/or start assembler coderoutines.

Graphical Programming:

microcontrollers, Parallax Propeller microcontroller, Multi-core architecture of Parallax Propeller, Speed and power management , On-board peripherals, ROM extensions , Built in SPIN byte code interpreter , Example program , Package and I/O , Dedicated cores instead of interrupts

Graphical programmin





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